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i5., laquo; deg;r fnnRHJ multiplier, пат. США,

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К i 1 b u г n Т. et al.. Improvements in orrelating to multiplying arrangements for digital computing and like purposes, англ. пат., кл. G4A (G06f), No 976620.

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je V i e n R. E., Determining best ordering of variables in casca-,:tching circuits. ((Switching Circuits Theory and Logical Design raquo;, des*

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L i n g Н., High speed binary paraller adder, laquo;1ЕЕЕ Trans. Electron. Comput. raquo;, 1966, 15, N 5, стр. 799-802.

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L i u С. N., A state variable assignment method for asinchronous sequental switching circuits, laquo;Journ. Assoc. Comput. Mach. raquo;, 1963, 10, N 2, стр. 209-216.

LoeliM., RosenfeldG., Logical design of ternary switching-circuits, laquo;1ЕЕЕ Trans. Electron. Comput. raquo;, 1965, 14, N i, стр. 19-29.

LoomisH. H., Jr., WymanR. H., Jr., On complete sets of logic primitives, laquo;1ЕЕЕ Trans. Electron. Comput. raquo;, 1965, 14, N 2, стр. 173-174.

Mac Sorley O. L., Binary divider, пат. США, кл. 235-164, № 3192364.

М a j e г s к i S., On determination of optimal distributions of carry skips in adders, laquo;1ЕЕЕ Trans. Electron. Comput. raquo;, 1967, 16, N 1, стр. 45-58.

M a j e r s к i S., W i w e g e r M., NOR-gate binary adder with carry completion detection, laquo;1ЕЕЕ Trans. Electron. Comput. raquo;, 1967, J6, N 1, стр. 90-92.

M a 1 e у G. A., Full adder and substractor using NOR logic, пат. США, кл. 235-176, № 3074640.

М a n о М. М., Converting to NOR and NAND logic, laquo;Electro-Technology raquo;, 1965, 75, N 4, стр. 34-37.

M a r t i n Y., Vo i t e 1 K., Rechenanordnung zur Multipliltati-on zweier positiver Zahlen, пат. ФРГ, кл. 42m, 14 (G06f), № 115873.

M a r t i n A. R., R о s e n s t e i n A. В., Shiftrix for high-speed multiplication, laquo;1ЕЕЕ Trans, on Electron. Comput. raquo;, 1965, vol. EC - 14, N 4. .

McCluskeyE.J., Logical design theory of NOR gate networks with no completented inputs, laquo;1ЕЕЕ - Switching circuit Theory and Logical Design*, 4th Annual Symposium - Special Publ. S-156, oct. 1963, стр. 137-148.

M с L a n e G. F., Multioperture plate half adder., пат. США, кл. 307-88, № 3243599.

McLaneG. F., Multioperture plate logic, пат. США, кл. 340-174, №3253268.

М e g g i t J. е., Pseudo division and pseudo multiplication processes, laquo;IBM Y. Res. and Developm. raquo;, 1962, 6, N 2, стр. 210-226.

MendelsonM. J., Apparatu.4 for performing arithmetic operations, пат. США, кл. 235-155, № 3018955.

М e г n e г J. N., Digital divider for integer and remainder division operations, пат. США, кл. 235-160, № 3254204.

Merriam Ann S., Asynchronous binary counter circuits, пат. США, кл. 328-41, № 3238461.

М e о A. R., Sulla sintesi di reti NAND NOR a molti livelli, laquo;Calcolo raquo;, 1965, 2, N 1, стр. 1-82.

Merrill R. D. Jr., Improving digital computer performance using residue number theory, laquo;1ЕЕЕ Trans. Electron. Comput raquo; 1964 13, N 2, стр. 93-101.

M e t z G. F., Digital comparator, nar. США, кл 340-146 2 № 3217293.

М e t z e G. F., Class of binary divisions yielding minimally represented quotients, laquo;IRE Trans. Electronic Comput. raquo; 1962 11 N6 стр. 761-764

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М i 1 1 e г W. S., Electronic gang switching system, пат. США кл 235-164, № Re 25724.

MinesH. W., Binary counter circuit, пат. США, кл. 235-179 №3141966.

М о г e 1 1 i S., S t e f a n e 1 1 i R., Alcuni circuiti contatori di tipo parallelo, laquo;Alta frequenza raquo;, 1965, 34, N 12, стр. 836-846.

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N a f f G. W., Y о u r к e H. S., Tunnel diode shift registers, пат. США, кл. 307-88.5, № 3209158.

NAND logic operation in serial adder circuits, laquo;Syst. Design.*,

1964, 8, N 4, стр. 8-9.

Nandi S. K., Krishnamurthy E. V., A simple technique for digital division, laquo;Communs. АСМ raquo;, 1967, 10, N 5, стр. 299- 301.

NashelskyL., Digital computer theory. S. 1, John Wiley and Sons, 1966, стр. 321.

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N e w m a n E. A., S t r i n g e r Y. В., Electrical digital computing engines, англ. пат., кл. 106 (1), № raquo; 907381.

N e w t о n Y. D., Core counter, пат. США, кл. 340-174, № 3181130.

N u t a 1 1 Y., Computer process for conversion of binary-coded decimal numbers to pure binary form, laquo;Radi6 and Electronic Engr. raquo;,

1965, 30, N 5, стр. 317-318.

О m a n R. M., Fast multiply system, пат. США, кл. 235-164, № 3192367.

Operateur arithmetique pour calculateur numerique, фр. пат., кл. G06b. № 1376559.

OsofskyH., Parallel adder circuit with impoved carry circuitry, пат. США, кл. 235-175, № 3234371.

OttawayG. et al.. Quotient guess divider, пат. США, кл. 235-156, № 3234367.

О w e n С. е.. Improvements in data storage or code conversion arrays, англ. пат. кл. G4A (G06f), № 976169.

Parallel and concurrent computer systems (Sympos. Summary), laquo;Proc. FIP Congr., New York City, 1965, vol 2 raquo;, Washington, D. C, Spartan Books, 1966, стр. 319-322.